EDN

How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)

This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various “sleep modes” used by non-volatile FPGAs. Low power CPLDs with I/O gating have many ...
EDN

Tools expand support for CPLD and FPGA development

Altium has expanded support for system-level FPGA and CPLD development by adding a JTAG interface to its Nexar system. The addition of the JTAG port enables engineers to use their FPGA-development ...
Electronic Design

CPLD And FPGA Families Add New Members

Adding to the CoolRunner-II CPLD family, the XC2C32A and XC2C64A debut in smaller MLF packages than their predecessors and integrate an additional I/O bank to support voltage level translation and ...
Embedded

Leveraging FPGA and CPLD digital logic to implement analog to digital converters

Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function ...
Electronic Design

Demo Platform Compares FPGA/CPLD Power

If you've ever wondered which FPGA/CPLD vendor offers the best performance at the lowest power, consider QuickLogic's Power Comparison Resource Package. Along with a corresponding Web site, it ...
CU Boulder News & Events

FPGA Design for Embedded Systems Specialization

This online engineering specialization will help you gain proficiency in creating prototypes or products for a variety of applications using Field Programmable Gate Arrays (FPGAs). You will cover a ...